Integrated two-terminal device and logic device with compact interconnects having shallow via for embedded application
US9865649B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2016 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Aug 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Devices and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions and providing a plurality of interlevel dielectric (ILD) levels having tight pitch over the first and second regions of the substrate. An ILD level of which a two-terminal element disposed thereon corresponds to a first ILD level and its metal level corresponds to Mx, an immediate ILD level overlying the metal level Mx corresponds to a second ILD level includes via level Vx and metal level Mx+1 and the next overlying ILD level corresponds to a third ILD level includes via level Vx+1 and metal level Mx+2. The method includes forming a two-terminal device element is formed in between metal level Mx and via level Vx+1 in the first region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.