Integrated process and structure to form III-V channel for sub-7nm CMOS devices
US9865706B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 27, 2016 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Oct 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments described herein generally relate to methods and structures for forming precise fins comprising Group III-V elements on a silicon substrate. A buffer layer is deposited in a trench formed in the dielectric material on a substrate. An isolation layer is then deposited over the buffer layer. A portion of the isolation layer is removed allowing for a precisely sized Group III-V channel layer to be deposited on the isolation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.