Chip substrate and chip package module
US9865787B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2015 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Nov 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/855
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A chip substrate includes conductive portions, insulation portions, cavities and a heat dissipating portion. The insulation portions are alternately bonded to the conductive portions to electrically isolate the conductive portions. The lens insertion portions are formed on an upper surface of the chip substrate at a predetermined depth so as to extend across each of the insulation portions. Each of the lens insertion portions includes a predetermined number of straight sides and a predetermined number of arc-shaped corners formed in regions where the straight sides meet with each other. The cavities are formed inward of the lens insertion portions at a predetermined depth so as to extend across each of the insulation portions. The heat dissipating portion is bonded to a lower surface of the chip substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.