Methods of forming nanosheets on lattice mismatched substrates
US9870940B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2016 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | Jul 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3226
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming nanosheets for a semiconductor device are provided including providing a silicon on insulator (SOI) handle wafer, the SOT handle wafer including a silicon layer and a dielectric layer on the silicon layer; providing a first donor wafer; bonding the SOI handle wafer and the first donor wafer together to provide a bonded structure; debonding the bonded structure to provide an intermediate wafer including a plurality of silicon or non-silicon nanosheets and a plurality of dielectric layers alternately stacked; and bonding the intermediate wafer to a second donor wafer to provide a final wafer including a plurality of silicon or non-silicon layers and a plurality of dielectric layers alternately stacked, wherein the final wafer includes at least one more pair of silicon or non-silicon and dielectric layers than the intermediate wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.