Patent · US Active

Multi-level chip interconnect

US9871017B2 · kind B2 · utility

0Cited by

2References

32Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Peter Ossimitz · Munich, DE
Tobias Jacobs · Mannheim, DE

Key dates

Filing date	Jan 4, 2016
Grant date	Jan 16, 2018
Priority date	—
Expiry date	Jan 4, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2225/06513
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Representative implementations of devices and techniques provide optimized electrical performance of interconnectivity components of multi-layer integrated circuits (IC) such as chip dice, for example. Different layers of the multi-layer IC include contact terminals that may be used to connect to circuits, systems, and carriers external to the IC.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.