Through silicon via sharing in a 3D integrated circuit
US9871020B1 · kind B1 · utility
2Cited by
8References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2016 |
| Grant date | Jan 16, 2018 |
| Priority date | — |
| Expiry date | Jul 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure generally relates to semiconductor structures and, more particularly, to intelligent through silicon via sharing in 3D-IC integrated structures and methods of manufacture. The structure includes: a plurality of stacked dies each containing at least one macro device; and a layer structure positioned between the plurality of stacked dies which comprises a control structured to route signals between the at least one macro device of a first stacked die and the at least one macro device of a second stacked die of the plurality of stacked dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.