Addressing coupled noise-based violations with buffering in a batch environment
US9875326B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2015 |
| Grant date | Jan 23, 2018 |
| Priority date | — |
| Expiry date | Mar 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism is provided for addressing coupled noise-based violations. For each net in an integrated circuit (IC) design, a determination is made as to whether an associated delta wire delay is below a predetermined threshold. Responsive to the associated delta wire delay failing to be below the predetermined threshold, a subset of nets is formed. For each net in the subset of nets, a stage delay side model of the net is adjusted to emulate a noise impact on timing of the net and an optimization is applied using the stage delay side model of the net. A full retiming of the set of nets is then performed. For each net in the subset of nets a determination is made as to whether the net has degraded slack and, responsive to the net having degraded slack, the applied optimization is backed out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.