Patent · US Active

Comprehensive path based analysis process

US9875333B1 · kind B1 · utility

36Cited by

5References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Sourabh Kumar Verma · Sidhauli, IN
Naresh Kumar · Santa Clara, US
Ajay Tomar · Sidhauli, IN
Rakesh Agarwal · Palo Alto, US
Umesh Gupta · Clinton, US
Manish Bansal · Delhi, IN
Kaustav Guha · Savanuru, IN
Prashant Sethia · Noida, IN

Key dates

Filing date	Jan 19, 2016
Grant date	Jan 23, 2018
Priority date	—
Expiry date	May 1, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/3312
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The present disclosure relates to a system and method for electronic design automation. Embodiments may include receiving, using at least one processor, an electronic design and determining one or more graph based analysis (“GBA”) violating nodes associated with the electronic design. Embodiments may include identifying a non-covered violating node from the GBA violating nodes and determining a worst timing path through the non-covered violating node. Embodiments may further include invoking a path-based analysis (“PBA”) on the worst timing path and determining if the worst timing path satisfies the PBA analysis.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.