Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact
US9881123B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2016 |
| Grant date | Jan 30, 2018 |
| Priority date | — |
| Expiry date | Jun 30, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are provided for timing analysis of an electronic circuit design. A timing graph defines a plurality of timing paths through different subsections of the electronic circuit design. A timing window is defined for each of the nodes included in a timing path. At least one preliminary round of a predetermined signal integrity analysis is executed on the circuit design based on the timing windows to identify at least one pair of crosstalk-coupled victim and aggressor nodes. Each victim node's timing window is adaptively adjusted according to a predetermined timing property thereof. At least one primary round of the predetermined signal integrity analysis is executed on the electronic circuit design based in part on this adaptively adjusted timing window for each victim node to generate a delay, which is annotated to the timing graph. A predetermined static timing analysis is executed based on the delay-annotated timing graph.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.