Fully depleted silicon-on-insulator device formation
US9882005B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2015 |
| Grant date | Jan 30, 2018 |
| Priority date | — |
| Expiry date | Jun 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described. The method includes processing a silicon germanium (SiGe) layer disposed on an insulator layer to form gaps on a surface opposite a surface that is disposed on the insulator layer, each of the gaps extending into the SiGe layer to a depth less than or equal to a thickness of the SiGe layer, and forming a gate conductor over a region of the SiGe layer corresponding to a channel region of the pMOS. The method also includes performing an epitaxial process on the SiGe layer at locations corresponding to source and drain regions of the pMOS planar FDSOI device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.