Methods of forming EPI semiconductor material on the source/drain regions of a FinFET device

US9887094B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Yi Qi · Niskayuna, US
• Hsien-Ching Lo · Clifton Park, US
• Jianwei Peng · Daguantang, CN
• Yanping Shen · Saratoga Springs, US
• Hui Zhan · Shanghai, CN

Key dates

• Filing date: May 3, 2017
• Grant date: Feb 6, 2018
• Expiry date: May 3, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/011
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

One illustrative method disclosed includes, among other things, forming a fin spacer adjacent a lower portion of a fin that is comprised of a fin spacer material, forming a conformal layer of a second spacer material on the exposed sidewalls and the upper surface of the fin, on the fin spacer and adjacent a gate structure of the FinFET device, wherein the second spacer material is a different material than the fin spacer material, performing an etching process to remove the second conformal layer from above the fin spacer to thereby re-expose the sidewalls of the fin above the fin spacer and the upper surface of the fin while forming a gate spacer comprising the second spacer material adjacent the gate structure, and forming an epi semiconductor material on the exposed sidewalls and upper surface of the fins above the first fin spacer.