Backward compatibility testing of software in a mode that disrupts timing
US9892024B2 · kind B2 · utility
5Cited by
22References
134Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2015 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Nov 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device may be run in a timing testing mode in which the device is configured to disrupt timing of processing that takes place on the one or more processors while running an application with the one or more processors. The application may be tested for errors while the device is running in the timing testing mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.