Fast scan to detect bit line discharge time
US9892791B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2016 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Jun 16, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells that have been sensed to be in a conducting state while the word line is set to a voltage level for sensing erased memory cells. The threshold current may be set based on a chip temperature and/or a particular number of bit errors that occurred during a prior sensing operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.