Device and method for reducing contact resistance of a metal
US9892963B2 · kind B2 · utility
1Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2015 |
| Grant date | Feb 13, 2018 |
| Priority date | — |
| Expiry date | Oct 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an integrated circuit includes depositing a cap layer on a substrate; depositing a dielectric layer on the cap layer; and forming a trench in the dielectric layer. The method further includes depositing a tantalum nitride (TaN) layer on a sidewall of the trench such that the TaN layer has a greater concentration of nitrogen than tantalum. The method further includes depositing a tantalum (Ta) layer on the TaN layer using physical vapor deposition (PVD); and depositing a metal layer over the Ta layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.