Patent · US Active

Memory architecture having two independently controlled voltage pumps

US9899089B1 · kind B1 · utility

0Cited by

24References

17Claims

0Family size

Assignee

Cypress Semiconductor Corporation · US

Inventors

Ryan T. Hirose · Colorado Springs, US
Fredrick B. Jenne · Tracy, US
Vijay Raghavan · Colorado Springs, US
Igor G. Kouznetsov · San Jose, US
Paul Fredrick Ruths · Woodland Park, US
Cristinel Zonte · Colorado Springs, US
Bogdan I. Georgescu · Colorado Springs, US
Leonard Vasile Gitlan · Colorado Springs, US
James Paul Myers · Miami, US

Key dates

Filing date	Sep 24, 2013
Grant date	Feb 20, 2018
Priority date	—
Expiry date	Sep 24, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG11C16/32
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage node of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.