Semiconductor device and fabrication method thereof
US9899226B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2015 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Mar 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.