Fabrication method of packaging substrate
US9899235B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2016 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Oct 14, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49158
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.