Etch stop liner for contact punch through mitigation in SOI substrate
US9899257B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2017 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | Mar 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a shallow trench isolation (STI) in a semiconductor-on-insulator (SOI) substrate, including an etch stop liner, to mitigate punch through in SOI substrates is disclosed. The method may include providing an SOI substrate, forming an STI recess within the SOI substrate, forming a first STI dielectric fill within the STI recess wherein a top surface of the first STI dielectric fill is at a location above a top surface of the base substrate, forming a first etch stop liner on the first STI dielectric fill, and forming a second STI dielectric fill over the first etch stop liner. The first etch stop liner is configured so that portion of a contact opening later formed is positioned over the first etch stop liner such that the etch stop liner prevents punch through into the STI. The method may also include forming a second etch stop liner after forming the STI recess and before forming the first STI dielectric fill.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.