Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivity
US9899279B2 · kind B2 · utility
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25References
10Claims
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Key dates
| Filing date | Oct 17, 2014 |
| Grant date | Feb 20, 2018 |
| Priority date | — |
| Expiry date | May 31, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.