Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods

US9899479B2 · kind B2 · utility

Assignee

• ATOMERA INCORPORATED · US

Inventors

• Robert J. Mears · Wellesley, US
• Hideki Takeuchi · Sakaki, JP

Key dates

• Filing date: May 13, 2016
• Grant date: Feb 20, 2018
• Expiry date: May 13, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/856

Abstract

A semiconductor device may include a semiconductor substrate, and a plurality of field effect transistors (FETs) on the semiconductor substrate. Each FET may include a gate, spaced apart source and drain regions on opposite sides of the gate, upper and lower vertically stacked superlattice layers and a bulk semiconductor layer therebetween between the source and drain regions, and a halo implant having a peak concentration vertically confined in the bulk semiconductor layer between the upper and lower superlattices.