Storage module and method for datapath bypass
US9905314B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2014 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Dec 19, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage module and method for datapath bypass are disclosed. In one embodiment, a storage module begins to perform a read operation that reads a set of code words from the memory and attempts to perform an error detection and correction operation on one of the read code words. In response to determining that the code word has an uncorrectable error, the storage module reads the other code words in the set but bypasses the error detection and correction operation on those other code words. The code word that had the uncorrectable error and the other code words are re-read, wherein at least the code word with the uncorrectable error is re-read with a different read condition. The storage module then attempts to perform the error detection and correction operation on the re-read code words. Other embodiments are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.