Inverted-T shaped via for reducing adverse stress-migration effects
US9905509B2 · kind B2 · utility
3Cited by
6References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2014 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Aug 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor interconnect structure is formed as a via with an inverted-T shape to increase the reliability of the interface between the interconnect structure and an underlying electrically conductive, e.g., copper (Cu), layer of material. The inverted-T shape effectively increases a bottom critical dimension of the via, thereby reducing and/or eliminating via degradation of the interconnect structure caused by voids in the electrically conductive layer introduced during high-temperature or stress-migration baking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.