Insulated gate bipolar transistor with improved on/off resistance
US9905686B2 · kind B2 · utility
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1Claims
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Key dates
| Filing date | Mar 21, 2016 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Mar 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
Abstract
In a plane view of the front surface of the semiconductor substrate, the source region and the first contact region are arranged adjacent to each other in a direction along the gate trench in an area being in contact with a side surface of the gate trench, and the second contact region is arranged adjacent to the source region and the first contact region in an area apart from the gate trench. The impurity concentration of the first contact region is lower than the impurity concentration of the second contact region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.