Controlling telemetry data communication in a processor
US9910470B2 · kind B2 · utility
7Cited by
35References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2015 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Mar 1, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.