Hierarchically aware interior pinning for large synthesis blocks
US9910952B2 · kind B2 · utility
2Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2016 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Jun 30, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and a computer implemented method for interior pinning in a macro block of an integrated circuit are provided. The method includes receiving child level information of the macro block including at least a location of a logic leaflet, receiving parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer, and selecting a pin location based on the child level information and the parent level information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.