Metrology target identification, design and verification
US9910953B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2014 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Mar 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/30
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A metrology design and verification framework is provided, which includes methods and systems for metrology structure identification in an integrated circuit design data block, design rule checking, hierarchal design of metrology target structures to minimize random errors, and metrology design rule verification of metrology target design files. In-die metrology targets are identified using various filtering methods and/or designed as hierarchical structure within dies or outside the dies. Particularly, metrology target design files are generated, which are hierarchical in structure and compatible with design rule checks. Design rule check takes into account the hierarchical and often repetitive target designs in the verification process. Layouts may be verified using design rule checks at different levels of design rules, which may be combined to remove rule violations and errors prior to actual target production.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.