Semiconductor memory device and writing operation method thereof
US9911498B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2017 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | May 5, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.