Cache memory diagnostic writeback
US9911508B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2014 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Jul 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a cache memory having a plurality of entries. Each of the entries holds data of a cache line, a state of the cache line and a tag of the cache line. The cache memory includes an engine comprising one or more finite state machines. The processor also includes an interface to a bus over which the processor writes back modified cache lines from the cache memory to the system memory in response to encountering an architectural writeback and invalidate instruction. The processor also invalidates the state of the entries of the cache memory in response to encountering the architectural writeback and invalidate instruction. In response to being instructed to perform a cache diagnostic operation, for each entry of the entries, the engine writes the state and the tag of the entry on the bus and does not invalidate the state of the entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.