Vertical-transport field-effect transistors with a damascene gate strap

US9911738B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Hiroaki Niimi · Cohoes, US
• Kwan-Yong Lim · Plano, US
• Brent A. Anderson · Jericho, US
• Junli Wang · Slingerlands, US

Key dates

• Filing date: May 4, 2017
• Grant date: Mar 6, 2018
• Expiry date: May 4, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

Methods for forming a structure that includes vertical-transport field-effect transistors and structures that include vertical-transport field-effect transistors. A first semiconductor fin is separated from a second semiconductor fin by a gap. A gate stack is conformally deposited that extends across the first semiconductor fin, the second semiconductor fin, and the gap. A section of the gate stack is located in the gap. A gate strap layer is formed in the gap on the section of the gate stack. The gate stack is patterned to form a first gate electrode associated with the first semiconductor fin and a second gate electrode associated with the second semiconductor fin. The gate strap layer masks the section of the gate stack when the gate stack is patterned. The first gate electrode is connected with the second gate electrode by the gate strap layer and the section of the gate stack.