Method, apparatus, and system having super steep retrograde well with engineered dopant profiles
US9911740B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2016 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Jul 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/22
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.