Non-volatile memory device and manufacturing method thereof
US9911847B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2017 |
| Grant date | Mar 6, 2018 |
| Priority date | — |
| Expiry date | Jul 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A non-volatile memory device includes a substrate, a gate stack structure, an erase gate structure, and a ferroelectric layer. The gate stack structure is disposed on the substrate. The erase gate structure is disposed on the substrate and disposed at a first side of the gate stack structure. The ferroelectric layer is disposed on a sidewall of the gate stack structure, and the ferroelectric layer is disposed between the gate stack structure and the erase gate structure. The ferroelectric layer disposed between the gate stack structure and the erase gate structure may be used to forma negative capacitance effect for amplifying the voltage applied to the erase gate structure. The purpose of reducing power consumption may be achieved accordingly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.