Method and apparatus for performing a bus lock and translation lookaside buffer invalidation
US9916243B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2014 |
| Grant date | Mar 13, 2018 |
| Priority date | — |
| Expiry date | Mar 4, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.