Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory
US9916257B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2011 |
| Grant date | Mar 13, 2018 |
| Priority date | — |
| Expiry date | Feb 3, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.