Nucleation layer for growth of III-nitride structures
US9917156B1 · kind B1 · utility
2Cited by
49References
40Claims
0Family size
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Key dates
| Filing date | Sep 2, 2016 |
| Grant date | Mar 13, 2018 |
| Priority date | — |
| Expiry date | Sep 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/854
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Nucleation layers for growth of III-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate. The nucleation layer can include silicon and deep-level dopants. The semiconductor can include a III-nitride layer formed over the nucleation layer. At least one of the silicon substrate and the nucleation layer can include ionized contaminants. In addition, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.