Device contact structures including heterojunctions for low contact resistance
US9917158B2 · kind B2 · utility
1Cited by
13References
16Claims
0Family size
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Key dates
| Filing date | Nov 16, 2015 |
| Grant date | Mar 13, 2018 |
| Priority date | — |
| Expiry date | Nov 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device can include a channel region with a first semiconductor material for a majority carrier in the channel region during operation (on state) of the device and a metal contact. A source/drain region can include a semiconductor material alloy including a second semiconductor material and at least one heterojunction located between the metal contact and the channel region, wherein the heterojunction forms a band-edge offset for the majority carrier that is less than or equal to about 0.2 eV.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.