Computer implemented system and method for reducing failure in time soft errors of a circuit design
US9922152B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 23, 2016 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | Apr 3, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented system and method is provided for reducing failure-in-time (FIT) errors associated with one or more sequential devices of a circuit design for a process technology. The method comprises receiving an input data file that includes register transfer level (RTL) data of the circuit design. The RTL data includes the one or more sequential devices. The method further comprises identifying a preferred logic state for each sequential device of the one or more sequential devices. The method further comprises adjusting the one or more sequential devices based on the preferred logic state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.