Gate patterning for AC and DC performance boost
US9923076B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 17, 2016 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | Jun 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method to reduce parasitic capacitance in a high-k dielectric metal gate (HKMG) transistor with raised source and drain regions (RSD) is provided including forming a multilayer stack for an HKMG gate on a substrate, the multilayer stack including a gate electrode layer of amorphous silicon or polycrystalline silicon, forming a patterned hard mask above the gate electrode layer, etching partially into the gate electrode layer through the patterned hard mask to define multiple partially etched gate stacks and a partially etching gate electrode layer, forming a conformal protective layer wrapping over the partially etched gate electrode layer and the patterned hard mask, and etching through a remainder of the partially etched gate electrode layer with the conformal protective layer wrapped over the partially etched gate stacks and the patterned hard mask, as well as an HKMG transistor resulting therefrom.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.