Low power barrier modulated cell for storage class memory
US9923140B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2016 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | Sep 20, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for providing a Barrier Modulated Cell (BMC) structure that may comprise a reversible resistance-switching memory element within a memory array are described. The BMC structure may include a barrier layer comprising a layer of amorphous germanium or amorphous silicon germanium paired with a conductive metal oxide, such as titanium dioxide (TiO2), strontium titanate (SrTiO3), or a binary metal oxide. The BMC structure may include a conductive metal oxide in series with an amorphous layer of a low bandgap material. The low bandgap material may comprise a semiconductor material with a bandgap energy (Eg) less than 1.0 eV. The improved BMC structure may be used for providing multi-level memory elements within a three dimensional memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.