Patent · US Active

Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry

US9923579B2 · kind B2 · utility

1Cited by

9References

13Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Michael Fee · Cold Spring, US
Ronald J. Frishmuth · Poughkeepsie, US
Mary P. Kusko · Poughkeepsie, US
Cedric Lichtenau · Stuttgart, DE

Key dates

Filing date	Mar 8, 2016
Grant date	Mar 20, 2018
Priority date	—
Expiry date	Apr 16, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/3602
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Aspects include techniques for implementing a clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry for encoding and correction of a chip. A computer-implemented method may include initializing a scan of the chip including data and a set of check bits protecting the data; applying a global control bit to a latch on the chip; and applying an additional clock to the latch so the check bits are updated using the on-chip circuitry.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.