Scaling multi-core neurosynaptic networks across chip boundaries
US9924490B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2013 |
| Grant date | Mar 20, 2018 |
| Priority date | — |
| Expiry date | May 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W64/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention provide a system for scaling multi-core neurosynaptic networks. The system comprises multiple network circuits. Each network circuit comprises a plurality of neurosynaptic core circuits. Each core circuit comprises multiple electronic neurons interconnected with multiple electronic axons via a plurality of electronic synapse devices. An interconnect fabric couples the network circuits. Each network circuit has at least one network interface. Each network interface for each network circuit enables data exchange between the network circuit and another network circuit by tagging each data packet from the network circuit with corresponding routing information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.