Erase stress and delta erase loop count methods for various fail modes in non-volatile memory
US9934872B2 · kind B2 · utility
41Cited by
112References
26Claims
0Family size
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Key dates
| Filing date | Oct 30, 2014 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Oct 15, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are presented for using erase stress and variations in the loop count (number of cycles) for various fail modes in non-volatile memories, including erase disturb and shallow erase. For detection of shallow erase, cells are programmed and then erased, where the variation (delta) in the number of erase loop counts can be used to determine defective blocks. To determine blocks prone to erase disturb, an erase stress is applied to unselected blocks, after which they are programmed: after then erasing one block, the next block can then be read to determine whether it has suffered erase disturb.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.