Method for evaluating a semiconductor wafer
US9935021B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 14, 2014 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Nov 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/125
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for evaluating a semiconductor wafer including preparing a reference wafer in which contamination element and amount of contamination are known, forming a plurality of cells including p-n junctions on the reference wafer, measuring junction leakage currents in the plurality of cells on the reference wafer to acquire a distribution of the junction leakage currents of the reference wafer, associating the distribution of the junction leakage currents of the reference wafer with a contamination element, forming a plurality of cells including p-n junctions on a wafer to be measured, measuring junction leakage currents in the plurality of cells on the wafer to be measured to acquire a distribution of the junction leakage currents of the wafer to be measured, and identifying a contamination element of the wafer to be measured based on the association.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.