CMOS FinFET device with dual strained cladding layers on relaxed SiGe fins, and method of fabricating the same

US9935107B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Stephen M. Cea · Hillsboro, US
• Roza Kotlyar · Portland, US
• Harold W. Kennel · Portland, US
• Kelin J. Kuhn · Beaverton, US
• Tahir Ghani · Portland, US

Key dates

• Filing date: Dec 16, 2013
• Grant date: Apr 3, 2018
• Expiry date: Dec 16, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

Techniques and methods related to dual strained cladding layers for semiconductor devices, and systems incorporating such semiconductor devices.