FinFET with source/drain structure
US9935199B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2016 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Apr 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate including a first fin element, a second fin element, and a third fin element. A first source/drain epitaxial feature is disposed over the first and second fin elements. A first portion of the first source/drain epitaxial feature disposed on the first fin element and a second portion of the first source/drain epitaxial feature disposed on the second fin element merge at a merge point. A second source/drain epitaxial feature is disposed over the third fin element. A first sidewall of the second source/drain epitaxial feature interfaces a first third-fin spacer disposed along a first sidewall of the third fin element. A second sidewall of the second source/drain epitaxial feature interfaces a second third-fin spacer disposed along a second sidewall of the third fin element. The merge point has a first height less than a second height of the first third-fin spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.