Systems and methods involving pseudo complementary output buffer circuitry/schemes, power noise reduction and/or other features
US9935635B2 · kind B2 · utility
24Cited by
3References
16Claims
0Family size
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Key dates
| Filing date | Aug 26, 2016 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Aug 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0185
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system may include a first inverter configured to invert a first data signal and a second inverter configured to invert a second data signal. A pull-up element may be coupled to an output of the first inverter on a first terminal and a power source on a second terminal, wherein the power source is also coupled to a pull-up element of a main output buffer. A pull-down element may be coupled to an output of the second inverter on a first terminal and a ground on a second terminal, wherein the ground is also coupled to a pull-down element of the main output buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.