Computer processor with register direct branches and employing an instruction preload structure
US9940129B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2016 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | May 17, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer processor with register direct branches and employing an instruction preload structure is disclosed. The computer processor may include a hierarchy of memories comprising a first memory organized in a structure having one or more entries for one or more addresses corresponding to one or more instructions. The one or more entries of the one or more addresses may have a starting address. The structure may have one or more locations for storing the one or more instructions. The computer processor may include one or more registers to which one or more corresponding instruction addresses are writable. The computer processor may include processing logic. In response to the processing logic writing the one or more instruction addresses to the one or more registers, the processing logic may to pre-fetch the one or more instructions of a linear sequence of instructions from a first memory level of the hierarchy of memories into a second memory level of the hierarchy of memories beginning at the starting address. At least one address of the one or more addresses may be the contents of a register of the one or more registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.