Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array
US9940302B2 · kind B2 · utility
4Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2016 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | May 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06593
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One embodiment comprises multiple semiconductor dies and at least one interconnect circuit for exchanging signals between the dies. Each die comprises at least one processor core circuit. Each interconnect circuit corresponds to a die of the processor array. Each interconnect circuit comprises one or more attachment pads for interconnecting a corresponding die with another die, and at least one multiplexor structure configured for exchanging bus signals in a reversed order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.