Editing a NoC topology on top of a floorplan
US9940423B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2015 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Dec 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NoC topology is represented on top of a physical view of a chip's floorplan. The NoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of switches within the floorplan is automatically computed. Locations can also be edited by a user. Statistical metrics are calculated, including wire length, switch area, NoC area, and maximum signal propagation delay for logic in each of multiple clock domains. Wire density can also be overlaid on chip's floorplan on the display. The NoC topology is represented by a data structure indicating connections between initiator and target endpoints with ordered lists of switches in between. The data structures are written and read from memory or a non-transient computer readable medium. The locations of endpoint and switches are also written out, as scripts for place & route tools.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.