Method and structure for minimizing fin reveal variation in FinFET transistor
US9941150B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2017 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Apr 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device includes forming a plurality of stacked portions spaced apart from each other on a substrate, each of the plurality of stacked portions including a semiconductor fin, a dielectric layer on the semiconductor fin, and a polymer layer on the dielectric layer. The method also includes forming an inter-level dielectric layer on the substrate between the plurality of stacked portions, forming a doped region in the inter-level dielectric layer at a depth below a top surface of the inter-level dielectric layer, and recessing the inter-level dielectric layer down to the doped region to form a plurality of isolation regions between the plurality of stacked portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.