Method for fabricating LDMOS with reduced source region
US9941171B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2016 |
| Grant date | Apr 10, 2018 |
| Priority date | — |
| Expiry date | Nov 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device including: forming a block layer above a well region of a first doping type in a semiconductor substrate, wherein the block layer has an opening for defining a first region in an upper part of the well region and has sidewalls at sides of the opening; implanting dopants of a second doping type into the well region through the opening of the block layer to form the first region; implanting dopants of the first doping type into the first region in the manner of large-angle-tilt dopants implantation to form a second region for a first transistor, and to form a third region for a second transistor; and forming, for both of the first transistor and the second transistor, a fourth region between the second region and the third region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.